A-SOUL is a fully functional out-of-order RISC-V CPU inspired by the MIPS R10K microarchitecture, featuring a unified RTL-level microarchitecture and a highly modular pipeline design. The project implements n-way superscalar execution, register renaming, speculative load scheduling, precise states, and early branch resolution within a synthesizable SystemVerilog framework.

The processor pipeline supports instruction-level parallelism with a multi-issue dispatch stage, a Reservation Station and Reorder Buffer, and a Load-Store Queue (LSQ) capable of byte-level forwarding and non-blocking memory access through an MSHR-based D-Cache. The instruction side incorporates GShare and Tournament branch predictors, return address stack, and a configurable adaptive instruction prefetcher with victim cache for reducing i-cache misses.

To improve performance, we designed a speculative LSQ that issues loads before dependent stores are fully resolved, reducing pipeline stalls caused by load/store dependency chains. This optimization alone improved CPI by 0.15 (≈ 8.1%) and eliminated 21 % of issue-stage stalls, bringing the overall average CPI down to ~1.7 at a 7.7 ns clock period after timing closure.

Beyond RTL design, the project features a robust testing and profiling infrastructure. We developed a top-down, counter-based performance simulator and an automated experiment pipeline for architectural design-space exploration. The framework systematically sweeps key microarchitectural parameters, collects CPI, occupancy, and stall breakdowns, and generates detailed visualizations for bottleneck identification and performance analysis. These tools enabled iterative optimization of critical paths (e.g., ROB/RS sizing, pipeline partitioning) and empirical validation across 20+ C benchmarks against a verified in-order golden model.

WriteBoost RCU extends the classic Read-Copy-Update (RCU) synchronization mechanism by integrating update-side coordination into the library, eliminating the need for external locks. Compared to liburcu and Folly RCU, it maintains RCU's wait-free reads while simplifying writer logic and improving throughput in balanced workloads.

The design introduces a single updater/reclaimer model, batch update processing, and an object pool for memory reuse—together removing retirement-list contention and amortizing copy costs. An epoch-based reader–reclaimer synchronization scheme ensures safe reclamation with amortized O(1) complexity and zero reader contention.

Evaluated against existing RCU and mutex-based mechanisms, WriteBoost RCU achieved 3.49 B reads/s and 35 M writes/s (8 thread), outperforming Folly RCU by ~1.8× on reads and maintaining competitive write performance. The project demonstrates that RCU can scale effectively beyond read-heavy workloads, combining high programmability with robust multi-core efficiency.