Experience and Publications
Domain-Specific Hardware
Application-Specific Integrated Circuit (ASIC)
Mozart introduces a chiplet ecosystem–accelerator co-design framework that constructs low-cost bespoke ASICs (BASICs) by leveraging operator-level disaggregation and composing accelerators from a reusable chiplet pool, thereby amortizing non-recurring engineering (NRE) costs while preserving high performance.
During the first half of 2025, I co-developed Mozart, a cross-layer co-design framework that rethinks how modern AI accelerators are built. The project was motivated by a key challenge in AI hardware: traditional monolithic ASICs are efficient but expensive to customize, while general-purpose accelerators lack specialization.
To address this, we combined operator-level disaggregation—which maps each neural operator to its most suitable compute and memory subsystem—with chiplet ecosystem co-design that identifies a minimal, reusable pool of chiplets to amortize the non-recurring engineering (NRE) cost of custom silicon. This combination allows bespoke accelerators to achieve both architectural efficiency and economic scalability.
At its core, Mozart employs a hierarchical optimization framework integrating simulated annealing, genetic algorithms, convex-hull–based layer mapping, and constraint programming. Together, these layers co-optimize chiplet selection, tensor fusion, software mapping, and physical design validation under unified energy, latency, and cost objectives—bridging architectural insight with manufacturable, sustainable AI hardware design.
Through this project, I gained a deep understanding of dataflow accelerator such as Eyeriss and Simba, as well as mapping-space explorer like Timeloop and Scale-sim. Working on Mozart allowed me to see how design space exploration (DSE) connects architectural abstraction, hardware constraints, and algorithmic optimization into a unified process. It trained me to reason about hardware not just in terms of microarchitecture, but as a multidimensional search problem—balancing performance, energy, and cost under real physical design limits. This experience laid the methodological foundation for my subsequent research in ISA-hardware co-design and domain-specific architecture exploration.
Publications
- Haoran Jin, Jirong Yang, Yunpeng Liu, Barry Lyu, Kangqi Zhang, Nathaniel BleierArXiv preprint; Under Review at MICRO
Application-Specific Instruction-set Processor (ASIP)
This project is an ISA–hardware co-design framework that uses e-graph rewriting at the assembly level to derive minimal, application-specific ISA subsets and guide circuit pruning under ISA-aware formal constraints for efficient ASIP generation.
Since the summer, I have been working with Prof. Nathaniel Bleier and Ph.D. student Haoran Jin on formal verification methods for external don't-cares. We soon realized that this domain is already quite mature, leaving limited space for new contributions. Around that time, I was introduced to e-graphs and Prof. Bleier's prior work on Property-Driven Automatic Transformation (PDAT), which ultimately inspired my honors thesis project.
My honors thesis aims to achieve application-specific ISA subset customization through assembly-level rewriting, followed by constraint-driven hardware trimming under ISA-aware synthesis. The project adopts an ISA–hardware co-design methodology, representing the first attempt to apply e-graphs directly at the assembly level.
Building on PDAT's property-driven foundation, we integrated induction-based signal correspondence to prune irrelevant or unreachable circuits. This enhancement delivers over 100× faster runtime while maintaining—or even improving—the result quality compared to the original PDAT framework.
Importantly, the system is designed as a general co-design framework, rather than a fixed ASIP generator for a single workload. Once an ISA subset is derived for Application A, the same subset can be used to rewrite and deploy Application B, effectively amortizing the non-recurring engineering (NRE) cost. The framework enables designers to explore Pareto-optimal ISA subsets across performance, power, and area, supporting scalable and workload-aware hardware customization.
This project deepened my understanding of traditional computer architecture while revealing that cross-layer co-design principles—often emphasized in modern AI infrastructure—can also advance conventional architectures. It has encouraged me to think about systems holistically, recognizing how interactions across abstraction layers shape performance, scalability, and efficiency.
Publications
- æSIP: µArch-aware ASIP-ISA Co-Design via Program Synthesis, Equality Saturation, and External Don’t CaresHaoran Jin*, Jirong Yang*, Barry Lyu, Ruijie Gao, Nathaniel Bleier (*Equal contribution, alphabetical order)ISCA 2026
- Scalable Hardware Pruning through Semiformal Verification and Microarchitecture AwarenessPlease reach out to me if you are interested in reading the full paper or slides.Second author; Under Review at ICCAD
Application
Agent
Beginning in 2024, I began exploring the potential of LLM agents in problem solving, deep semantic understanding over long contexts, and modeling human behavior within transportation systems. Over time, this exploration led me to shift my focus toward computer architecture.
This is an era defined by artificial intelligence. With the rapid evolution of large language models (LLMs), the boundary between humans and intelligent agents is being continuously reshaped. The release of Stanford's Smallville (Generative Agents, 2023) sparked widespread discussion, drawing attention to LLM-based agents and their potential to reason, plan, and interact like humans. I was no exception.
Beginning in 2024, I started exploring the potential of LLM agents—not only in problem solving, but also in deep semantic understanding over long contexts and in modeling human behavior within transportation systems.
LLMs are transforming the world around us, quietly integrating into our everyday lives. In certain domains, they have already surpassed human performance, yet they still fall short of the ideal artificial general intelligence (AGI) we aspire to build. Motivated by this, I gradually shifted my focus toward computer architecture, aiming to contribute to the foundational infrastructure that empowers the next generation of AI. At the same time, I closely follow cutting-edge AI directions such as neuro-symbolic reasoning and embodied intelligence.
To me, the future of AI is not only about smarter algorithms, but also about efficient and sustainable systems that truly support them.
Publications
- Tianming Liu, Jirong Yang, Yafeng YinArtificial Intelligence for Transportation, 2025
- Tianming Liu, Jirong Yang, Yafeng Yin, Manzi Li, Linghao Wang, Zheng ZhuPreprint; Major Revision, Transportation Research Part C: Emerging Technologies
- LiveOIBench: Can Large Language Models Outperform Human Contestants in Informatics Olympiads?Kaijian Zou, Aaron Xiong, Yunxiang Zhang, Xinliang Frederick Zhang, Yueqi Ren, Jirong Yang, Ayoung Lee, Shitanshu Bhushan, Lu WangUnder Review at ICML 2026