Experience and Publications

Domain-Specific Hardware

Application-Specific Integrated Circuit (ASIC)

Mozart introduces a chiplet ecosystem–accelerator co-design framework that constructs low-cost bespoke ASICs (BASICs) by leveraging operator-level disaggregation and composing accelerators from a reusable chiplet pool, thereby amortizing non-recurring engineering (NRE) costs while preserving high performance.

Publications

Application-Specific Instruction-set Processor (ASIP)

This project is an ISA–hardware co-design framework that uses e-graph rewriting at the assembly level to derive minimal, application-specific ISA subsets and guide circuit pruning under ISA-aware formal constraints for efficient ASIP generation.

Publications
  • æSIP: µArch-aware ASIP-ISA Co-Design via Program Synthesis, Equality Saturation, and External Don’t Cares
    Haoran Jin*, Jirong Yang*, Barry Lyu, Ruijie Gao, Nathaniel Bleier (*Equal contribution, alphabetical order)
    ISCA 2026
  • Scalable Hardware Pruning through Semiformal Verification and Microarchitecture Awareness
    Please reach out to me if you are interested in reading the full paper or slides.
    Second author; Under Review at ICCAD

Application

Agent

Beginning in 2024, I began exploring the potential of LLM agents in problem solving, deep semantic understanding over long contexts, and modeling human behavior within transportation systems. Over time, this exploration led me to shift my focus toward computer architecture.

Publications